In this paper. we present a RISC-V RV32I-based system-on-chip (SoC) design approach using the Vivado high-level synthesis (HLS) tool. The proposed approach consists of three separate levels: The first one is an HLS design and simulation purely in C++. The second one is a Verilog simulation of the HLS-generated Verilog implementation of the CPU core. https://www.spidertattooz.com/Kaiser-Copy-Stand-RS-1-with-RA-1-Arm-40-Counterbalanced-Column-and-18-x-20-Baseboard/